RAM512 Chip

1. RAM512 Chip

RAM512 is a memory chip that contains 512 16-bit registers, addressable by a 9-bit address. Internally, it is built from 8 RAM64 chips. The top 3 bits of the address (address[6..8]) select which RAM64 to activate, and the bottom 6 bits (address[0..5]) select the register within that RAM64.

2. Truth Table

address (9-bit)	in (16-bit)	load	out (16-bit)	Notes
000000000	0000000000000000	0	previous value	No update, reads old value
000000011	1111111111111111	1	1111111111111111	Writes to address 000000011
000000011	0000000000000000	0	1111111111111111	Reads stored value at 000000011
101101010	1010101010101010	1	1010101010101010	Writes to address 101101010
101101010	0000000000000000	0	1010101010101010	Reads stored value at 101101010

3. Implementation (HDL)

RAM512 is composed of 8 RAM64 chips. The upper 3 address bits (address[6..8]) are used to choose the active RAM64 chip, while the lower 6 bits (address[0..5]) address a register inside that chip.

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[6..8], a=la, b=lb, c=lc, d=ld, e=le, f=lf, g=lg, h=lh);

    RAM64(in=in, load=la, address=address[0..5], out=ra);
    RAM64(in=in, load=lb, address=address[0..5], out=rb);
    RAM64(in=in, load=lc, address=address[0..5], out=rc);
    RAM64(in=in, load=ld, address=address[0..5], out=rd);
    RAM64(in=in, load=le, address=address[0..5], out=re);
    RAM64(in=in, load=lf, address=address[0..5], out=rf);
    RAM64(in=in, load=lg, address=address[0..5], out=rg);
    RAM64(in=in, load=lh, address=address[0..5], out=rh);

    Mux8Way16(a=ra, b=rb, c=rc, d=rd, e=re, f=rf, g=rg, h=rh, sel=address[6..8], out=out);
}